REATISS Sample Preparation Lab is a laboratory specialized on integrated circuits package de-capsulation and die delayering. It is focusing on constant development of sophisticated sample preparation methods and techniques to meet growing complexity of technologies.

Specialized equipment, expertise in wet and plasma etching, as well as advanced methods of mechanical polishing allow the team to successfully work with all package types (BGA, FCBGA, QFN, SOP, WLCSP, PoP, SiP etc.) and with wide range of technologies (up to 5nm and beyond, including High-k metal gates, FinFET etc.).

The Lab is able to perform RE even on highly customized ‘One-of-a-Kind’ products, in cases when obtaining several part samples is not an option. Delayering and layer-by-layer imaging of the unique sample give a customer possibility to obtain vital business information.